During a circuit design process, a circuit designer may create an original circuit design, which may be modeled using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), Verilog or another suitable language. The original circuit design may be changed during the circuit design process. For example, a modified circuit design may increase reliability of the original circuit design by replacing each significant latch (e.g., a latch which drives a downstream logic value) with a plurality of latches, such as a three-latch latch set, thereby adding redundancy to the modified circuit design. The modified circuit design may also include voting or majority logic coupled to the latch set to ensure a majority value output from the latches of the latch set serves as the output of the latch set. Circuit design modifications such as this are often done to mitigate the effects of single event upsets (SEU's) that may occur in circuit designs without such modification. While designing the modified circuit, the modified circuit may be tested using modeling.
Boolean equivalency checking (BEC), also known as combinational equivalency checking, is a process employing formal mathematical methods to ensure that the modified circuit design is identical in function to the original circuit design. As a first phase of BEC between the two circuit designs, correspondence or mapping is performed. During mapping, corresponding logic cones are identified for the two circuit designs, respectively. Each logic cone may describe combinational logic having a plurality of inputs and an output. However, traditional correspondence or mapping may not enable accurate BEC. For example, traditional mapping of the modified circuit design that includes a three-latch latch set, may map each latch of the three-latch latch set to the corresponding latch in the original circuit design. Such a mapping causes each latch of the latch set to be treated as storing the same value (e.g., the value output from the corresponding latch in the original circuit design). Therefore, if such a traditional mapping is employed (without further modification of the modified circuit design model), BEC may be unable to detect errors within the voting logic, as the voting logic is never required to resolve a logic value from the latch set when errors are present within the latch set resulting from SEU's. Accordingly, improved methods and apparatus for BEC are desired.